The thermal behavior of a flip-chip laser array within a Photonics Integrated Circuit (PIC)

For telecommunications applications, Photonics Integrated Circuits (PICs) are currently under development in order to realize devices such as optical transmitters and receivers. PICs offer compelling advantages in terms of performance, miniaturization and - in some applications - energy efficiency. High-density PICs represent a significant thermal management challenge, however, particularly for laser arrays. These devices feature tight temperature limits (±0.1K), low operating temperatures (as low as 15-25°C), moderate heat loads (∼1-10W) but very high heat fluxes (over 100Wcm ^-2). Contemporary hybrid packaging strategies involve low profile (<1mm) multilayer substrates interposed between the devices (∼3x3mm) and thermo-electric modules (TEM) (∼30x30mm) which provide thermo-mechanical compatibility (with semiconductor materials), high thermal conductivity and electrical interconnection. These substrates are typically Aluminum Nitride (AlN) or silicon with metalized layers and plated vias. The theme of this paper is the interconnection details of a 'flip-chipped' laser array PIC to ensure adequate heat transfer into its carrier substrate. The objective is to understand the influence of three parameters; laser-to-laser spacing within the array, characteristics of the metallization geometries, and the location of heat generating passive devices adjacent to the PIC. Using finite element analysis (FEA), a set of coupled numerical models was created to capture the thermal behavior of a representative laser array within a flip-chip PIC. It was found that laser-to-laser spacing has a strong effect on the temperature distributions across the array; also the influence of adjacent passive devices has no significant bearing on the laser array temperature. This paper represents the initial results of an extensive programme of work on packaging-related aspects of next-generation PICs.