Two dimensional equalizer using parallel FIR filters for data storage

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper presents an efficient two dimensional equalizer architecture for data storage. Using parallel FIR structures with modulo arithmetic, the equalizer complexity is significantly reduced, while still operating with low latency. The architecture uses a combination of number theoretic transforms (NTTs) which perform better than conventional interpolation structures with decimation factors that are powers of 2 and 3. A key contribution to the reduction in complexity is the reuse of transform blocks.

Original languageEnglish
Title of host publication2007 IEEE International Conference on Communications, ICC'07
Pages6214-6219
Number of pages6
DOIs
Publication statusPublished - 2007
Event2007 IEEE International Conference on Communications, ICC'07 - Glasgow, Scotland, United Kingdom
Duration: 24 Jun 200728 Jun 2007

Publication series

NameIEEE International Conference on Communications
ISSN (Print)0536-1486

Conference

Conference2007 IEEE International Conference on Communications, ICC'07
Country/TerritoryUnited Kingdom
CityGlasgow, Scotland
Period24/06/0728/06/07

Fingerprint

Dive into the research topics of 'Two dimensional equalizer using parallel FIR filters for data storage'. Together they form a unique fingerprint.

Cite this